AI 芯片全景图 · 一片晶圆的旅程 · 2026-07 · 全产业链 + 地缘Semiconductors × AI · The Journey of One Wafer · Jul 2026 · Full chain + geopolitics

一个产业,两个市场 One industry, two markets

半导体正同时经历两场重构:AI 把需求曲线掰成了指数(2025 年全球销售额 7917 亿美元,+25.6%),地缘把效率最优的全球分工掰成了安全冗余。结果是「半导体周期」这个单数名词失效了——同一时刻,先进节点在配额制(CoWoS 售罄到 2027、交期 52–78 周),成熟节点在打价格战。而在两条主线之下还有一条更安静的线:芯片是 AI 设计 AI 的第一现场——英伟达买自家芯片驱动的 EDA 超算来设计下一代芯片,自指循环已经商业闭合;但它是加速器,不是自举机。 Semiconductors are being rebuilt twice at once: AI bent the demand curve into an exponent ($791.7B sales in 2025, +25.6%) while geopolitics bent the efficiency-optimal division of labour into security redundancy. The singular «semiconductor cycle» is dead — at this very moment advanced nodes run on quotas (CoWoS sold out through 2027, 52–78-week lead times) while mature nodes fight a price war. Beneath both runs a quieter line: chips are the first site where AI designs AI — Nvidia buys EDA supercomputers powered by its own silicon to design its next generation; the self-referential loop has commercially closed. It is an accelerator, not a bootstrap.

本图相信:AI 改造芯片业是真的——Synopsys DSO.ai 累计超 700 次流片优化;Cadence Cerebrus 具名客户 PPA 改善 4.4–20%;英伟达 NB-Cell 把 80 人月的单元库设计压缩到单卡一夜,ChipNeMo 服务 1.1 万名内部工程师;AI 相关芯片已占行业营收接近一半(B)。This map believes: AI is genuinely remaking chipmaking — Synopsys DSO.ai has run 700+ tape-out optimisations; Cadence Cerebrus posts named-customer PPA gains of 4.4–20%; Nvidia’s NB-Cell compresses 80 person-months of cell-library design into one GPU-night, and ChipNeMo serves 11,000 internal engineers; AI-related chips already take nearly half of industry revenue (B).
本图不相信:「AI 设计芯片已经端到端」。AlphaChip 至今无独立复现、没有任何商业 EDA 把它采纳进工具链;LLM 生成 RTL 的质量瓶颈被证明在规范而非模型(改写规范后 pass 率 55.8%→96%);「中微 5nm 通过台积电验证」「上海微电子 28nm 良率 90%」等广传消息无一获得一手证实(A/B)。It does not believe «AI designs chips end to end». AlphaChip has never been independently reproduced and no commercial EDA adopted it; LLM-written RTL bottlenecks on the spec, not the model (pass rates jump 55.8%→96% with better specs); and the viral claims about domestic 5nm etch validation or 28nm litho yields have zero first-hand confirmation (A/B).

主脊:一片晶圆的七站(设计 EDA/IP→代工制造→存储→设备与材料→封测→地缘战争→AI 造芯自指),②③标红;三条结构带:国产替代分层诚实账、生态 > 参数、管制时间线三判断;判断层:生态与软件 > 单点硬件参数——替代战争的正确打法是开放中间层+系统级补偿,不是一比一对标 CUDA。姊妹:算力的电与地→energy,终端入口→hardware,汽车芯片→car,制造业→factory The spine: one wafer, seven stations (EDA/IP → foundry → memory → tools & materials → packaging → the chip war → AI-designs-AI), ② and ③ in red; three bands: the layered honesty of substitution, ecosystem > specs, three readings of the control timeline; the judgment: ecosystem and software beat point hardware — the right substitution play is open middle layers plus system-level compensation, not a one-for-one CUDA clone. Sisters: energy, hardware, car, factory.

~50% : 0.2%
AI 相关芯片占行业总营收 vs 占总出货量——价值已完全 AI 化,物理体量仍由手机汽车工业撑着;做投资看前者,做供应链风控看后者(B)AI chips’ share of industry revenue vs shipments — the value is fully AI’d while the physical volume still rides phones and cars; invest by the former, manage supply risk by the latter (B)
72.3%
台积电 2026Q1 代工份额;HPC 平台占其营收 66%、手机降至 22%——「手机代工厂」已变身「AI 代工厂」,毛利率 67.7%(A/B)TSMC’s Q1-2026 foundry share; HPC is 66% of its revenue and phones just 22% — the phone foundry became the AI foundry, at 67.7% gross margin (A/B)
+93–98%
2026Q1 DRAM 合约价单季环比涨幅;手机存储成本占比从 10–15% 升至 30–40%——AI 数据中心的胃口,正通过存储价格向全谱系征税(A/B)Q1-2026 DRAM contract-price jump in one quarter; phone-memory cost share rose from 10–15% to 30–40% — the AI data centre’s appetite taxes everything through memory (A/B)
2026-11
未来 12 个月最重要的日历风险:穿透规则暂停至 11-09、镓锗锑禁令暂停至 11-27——两个暂停几乎同时到期,要么续期,要么同步回弹(A)The next year’s biggest calendar risk: the affiliates rule pauses until Nov 9 and the gallium bans until Nov 27 — both expire together: renew, or snap back in sync (A)
口径裁判:EDA 三巨头份额 60% 或 85% 取决于 TAM 定义;中国设备自给率三个口径(13.6%/35%/50%)相差近 4 倍,不应采信任一数字;美国人才缺口 6.7 万(SIA)vs 15.7 万(SEMI/NSF/麦肯锡)差一倍以上;四大云厂 capex 6900 亿 vs 7250 亿美元并列;「2026 年市场 1.5 万亿美元(+90%)」与 WSTS 9755 亿量级矛盾,判定为错误数据剔除;国产设备两条最广传的消息(中微 5nm 验证、SMEE 28nm)均无路透/彭博/日经/TechInsights 任何一家证实。Refereeing the numbers: EDA’s big-three share is 60% or 85% by TAM definition; China’s tool self-sufficiency spans 13.6%/35%/50% — trust none; the US talent gap is 67k (SIA) or 157k (SEMI/NSF/McKinsey); hyperscaler capex is $690B or $725B; the «$1.5T, +90%» market call contradicts WSTS’s $975.5B and is discarded as error; and the two most viral domestic-tool claims carry no confirmation from Reuters, Bloomberg, Nikkei or TechInsights.
中心装置 · 配额制与价格战同屏The central device · Quotas and price wars on one screen
「卖不出去的产能」和「排到 2027 年的交期」同时存在——用单一周期框架分析 2026 年的半导体,一定得出错误结论。«Unsellable capacity» and «lead times into 2027» coexist — a single-cycle frame guarantees the wrong 2026 conclusion.
先进侧:配额制The advanced side: quotas
CoWoS 产能「极度紧张、2026 年全部售罄」,三座后段厂交期排到 2027、周期 52–78 周,英伟达一家估计占用 60–70%;2nm 大芯片设计成本 7.25 亿美元、一座 2nm 厂 280 亿美元、单片晶圆 3 万美元。同时路线图集体后移:A16 推迟到 2027、三星 SF1.4 推迟到 2029、台积电 A12/A13 明确绕开 High-NA——微缩的经济性正在崩塌,路线图由「物理能做什么」改为「客户愿意为什么付钱」;英特尔那句「没有外部客户就不做 14A」是全行业最诚实的一句话CoWoS is «extremely tight, sold out for 2026» with back-end queues into 2027 at 52–78 weeks and Nvidia holding an estimated 60–70%; a 2nm flagship costs $725M to design, a fab $28B, a wafer $30k. Meanwhile the roadmaps slip in unison: A16 to 2027, SF1.4 to 2029, A12/A13 explicitly skipping High-NA — the economics of shrink are collapsing, and roadmaps now follow what customers will pay for; Intel’s «no external customer, no 14A» is the industry’s most honest sentence.
成熟侧:价格战与反转信号The mature side: price war, with a turn signal
中国大陆成熟制程产能 2027 年将占全球 33%,2030 年以 30% 的代工产能份额超过中国台湾;SiC 第一轮洗牌已出结果——技术领先者 Wolfspeed 死于扩产与降价的剪刀差(Chapter 11,债务削减 70%)。但 2026 年出现反转:8 英寸利用率回升至近 90%,代工厂开始涨价,大摩发布「成熟制程上升周期即将到来」。Nexperia 事件的教训同样属于这一侧:让本田停产、损失 1500 亿日元的,不是 3nm,是几毛钱一颗的分立器件。Mainland China holds 33% of mature capacity by 2027 and passes Taiwan in foundry share by 2030; SiC’s first shake-out has its verdict — leader Wolfspeed died in the scissors of expansion and price cuts (Chapter 11, debt cut 70%). Yet 2026 turned: 8-inch utilisation is back near 90%, foundries are raising prices, Morgan Stanley calls a mature-node upcycle. The Nexperia lesson belongs here too: what stopped Honda’s lines and cost ¥150B was not 3nm — it was a discrete part worth pennies.
判词Verdict过去 50 年,「更好的芯片」=「更小的晶体管」;未来 10 年,「更好的芯片」=「更小的晶体管 ×(更好的封装+更好的架构+更好的系统级互联)」,且后三项的边际贡献正在超过第一项——华为 CloudMatrix 以弱单芯片跑赢 NVL72 部分指标,是「系统级设计可以部分补偿工艺劣势」的现实证明,也是被管制一方最重要的战术出口。For fifty years «a better chip» meant «a smaller transistor»; for the next ten it means «a smaller transistor × (better packaging + better architecture + better system interconnect)» — with the latter three now contributing more at the margin. Huawei’s CloudMatrix beating NVL72 on some metrics with weaker dies proves system design partially offsets process deficits — the sanctioned side’s most important tactical exit.
Reading the Map

从这张图带走的五条规律Five patterns to take away

立场声明:本图为半导体产业与地缘的结构分析,不构成任何投资建议;全文不含任何规避出口管制的技术细节、采购路径或工艺配方;冲突数据一律并列呈现不做调和,凡未获第三方独立证实处均已标注;中文信源在国产设备/封测/EDA 上存在系统性正面偏差,本图已逐处打折;市场地图 ≠ 推荐背书;仅供研究与批判性参考。Stance: a structural read of the industry and its geopolitics — not investment advice; nothing here describes export-control evasion, procurement routes or process recipes; conflicting data are listed unreconciled, unverified claims flagged; Chinese-language sources carry a systematic positive bias on domestic tools which this map discounts throughout; a market map is not an endorsement; for research and critical reference only.